This section is intended to introduce the reader to various aspects of art, which may be related to various aspects of the present invention that are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Electronic circuits which are supplied an input signal at a certain clock frequency often need to process the received input signal in further processing stages. Therefore, fixed relationships between the clocks used inside the further processing stages and the input signal are required. A further requirement is that the clocks have a very low jitter, i.e., the very low fluctuations in frequency or phase. To this end the input signal is often supplied to a phase lock loop circuit, or PLL circuit, which synchronises a controllable oscillator with the input signal. One particular type of PLL circuits uses a temperature compensated voltage controlled oscillator (TCXO). TCXOs exhibit excellent temperature and jitter behaviour. Oscillators of this type, however, have a very small frequency pulling range, i.e. the output frequency of this type of oscillator only be changed within a small range around the nominal frequency. As a result, PLL circuits using TCXO oscillators have a very small locking range, i.e. the difference between the input signal frequency and the nominal frequency of the oscillator must not be very large. PLL circuits that have a larger locking range can be built using voltage controlled oscillators (VCXO), which have a larger pulling range. VCXOs, however, are less stable in frequency and phase compared to TCXOs and thus the output signal of a PLL circuit using VCXOs may have a higher amount of clock jitter compared to a PLL circuit using a TCXO.